The present invention relates generally to integrated circuit devices and, more particularly, to a single level of metal test structure for differential timing and variability measurements of integrated circuits.
Delays of individual logic gates in complementary metal oxide semiconductor (CMOS) technologies at the 45 nanometer (nm) technology node are on the order of about 10 picoseconds (ps) or less. Measuring delay characteristics of individual gates for monitoring technology performance and variability during process development and manufacturing is a challenging exercise. Typically, the average delay per stage is estimated from the frequency of oscillation of ring oscillators (RO) comprising an odd number of identical inverting stages. The RO frequency is divided so that the output is below 1 MHz for ease of measurement in the manufacturing line.
From this approach it is possible to determine the average of the pullup and pulldown delays of the gate running under steady-state (SS) conditions. It is often of importance to know the pullup and pulldown delays independently, both in SS as well as for different historical switching patterns. This is especially the case with partially depleted silicon on insulator (PDSOI) technology where the delay of a logic gate can vary by as much as 10% or more depending on the previous switching history of the gate, as mediated by the PDSOI floating body. In addition, with the ever continuing scaling of CMOS technologies, it is becoming increasingly important to be able to characterize the variability in gate delays and the AC matching characteristics of nominally identical devices.